The present invention relates to a computer implemented method, data processing system, and computer program product for making and/or using a special purpose adder, and more specifically to the design of the adder with associated signals and instructions to use the adder.
Most central processing units (CPU) provide general purpose arithmetic functions that sum two addends stored as binary numbers, per adder, at one time. Designers of such CPUs provide such a function since it can be implemented in a compact space on silicon or other substrates and permit a broad range of mathematical functions to be performed according to machine instructions. As such, the CPUs are used in a wide variety of arithmetic. The task of using the hardware efficiently is then handed over to software developers.
However, the dual input adders of the past suffer from the limitation that for large quantities of numbers that are to be summed together, the CPU must iterate on the order of logarithm base 2 of the quantity of numbers to be summed.